epc110 fully integrated configurable light barrier driver & receiver general description the epc110 is a general purpose, fully integrated self-contained cmos circuit to be used in light-barrier applications. the chip contains a controller which drives an led, typically an ir- led. the led is used in a pulsed mode to increase the signal-to- noise ratio even when there is very strong sunlight biasing the photo diode. it contains also a high sensitive photo diode amplifier and a signal conditioning circuitry to cancel unwanted environmental light including strong sunlight and pulsed light sources. the receiver is built around a synchronous demodulator circuitry. two output signals with different threshold levels are implemented in order to trigger the light barrier output or to indicate light reserve. the chip also includes a power supply circuitry to establish all internally required voltages from one source only. it can be used either as a standalone device, forming the whole core of an industrial light barrier. it can also be used together with a micro- controller ( m c) for more advance applications. features ? fully integrated light barrier chip ? needs just a photo diode and a led with a led driver ? customer c onfigurable version for i.e. high sensitivity or high speed applica tions ? integrated clock generator ? csp10 package with very small footprint or standard qfn16 package available applications ? light barriers ranging from millimeters to tens of meters ? smoke detectors ? liquid detectors functional block diagram for 10-pin chip scale package (for 16-pin qfn package) functional block diagram epc70x lst outh v o l t a g e r e g u l a t o r parameter memory interface outn so vdd33 pd 03.02.2011 page 1 file: unbenannt this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . led d1 v led f vdd18 signal processor processor spi controller gnd vdd led sck 9 (12) 10 (10) 7 (15) 4 (4) 1 (9) vdd33 2 (7) 8 (14) 3 (6) 5 (2) 6 (1) en si cs vdd prog sck figure 1 : block diagram configuration fix-parameter mode dynamic mode standalone epc110 m c --> spi --> epc110 internal controlled light barrier read rate controlled en --> epc110 m c --> spi / en --> epc110 external controlled light barrier read rate static parameters ambient adaptive reading application table 1 : configurations versus applications ? 2011 espros photonics corporation characteristics subject to change without notice 1 datasheet epc110 - v2.1 www.espros.ch
epc110 absolute maximum ratings (notes 1, 2) recommended operating conditions voltage at any pin except pin vdd -0.3v to v n +0.3 v min. max. units power supply voltage at pin vdd programming voltage at pin vdd -0.3v to +5.5v -0.3v to +8.0v operating supply voltage at vdd programming voltage at vdd 3.0 7.0 3.6 8.0 v v power supply voltage at pin vdd33 -0.3v to +5.5v operating supply voltage at vdd33 3.0 3.6 v output current at any pin except pin led -6ma to +6ma operating temperature (t o ) -40 +85 c power consumption with maximum load 125 mw lead temperature solder, 4 sec. (t l ) +260c humidity (non-condensing) +5 +95 % note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. recommended operating conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. for guaranteed specific - ations and test conditions, see electrical characteristics. note 2: this device is a highly sensitive cmos ac current amplifier with an esd rating of jedec hbm class 0 (<250v). handling and assembly of this device should only be done at esd protected workstations. electrical characteristics 3.0v < v n < 3.6v, -40c < t a < +85c, unless otherwise specified general data symbol parameter conditions/comments values units min. typ. max. v n operating power supply voltage at vdd33 (and vdd) 3 3.6 v pup power-up threshold voltage voltage at vdd33 when the device starts up 2.4 3 v v pp ripple on supply voltage, peak to peak input pulse i pd nst 36na 70 mv 48na 150 mv 72na 350 mv 108na 600 mv i n current consumption operating in operation mode, i pd = 0 ma, no load 2 ma i prog current consumption programming in program mode, vdd @ 8.0v, i pd = 0 ma, no load 4 ma v oh output high voltage except outh and led v n - 0.5v v v ol output low voltage @ 4ma source, including outh and led 0.5 v v hoh output high voltage outh see figure 8 v ledh output high voltage led @ 0.1ma sink current v n - 0.5v v i led source current maximum at pin led, v led @ 0... v n - 1.0v 0.7 1.3 ma v ih input high voltage 0.7*v n v n v v il input low voltage gnd 0.3*v n v i leakd input leakage current 10 a r pu pull-up resistor internal at digital input 30 200 k f clk reference clock of internal oscillator - for information only all internal timings are referenced to this clock 32 mhz d f clk temperature drift of the oscillator - for information only 640 ppm/k ? 2011 espros photonics corporation characteristics subject to change without notice 2 datasheet epc110 - v2.1 www.espros.ch
epc110 spi interface da ta (for more details refer to spi interface ) symbol parameter conditions/comments values units min. typ. max. f sck sck clock frequency 10 mhz t h high period of sck 50 ns t l low period of sck 50 ns t rf sck serial clock rise / fall time of sck 20 ns t 1 edge time cs --> sck 50 ns t su set-up time of si 15 ns t hold hold time of si 15 ns t d output data of so valid after sck 20 ns t rf output data rise / fall time of so 20 ns other data (refer to functional description ) symbol parameter conditions/comments para- meter values units min. typ. max. i pdn photo current sensitivity outn pulse height to trigger internal threshold outn . refer to functional description sensn programmable between 24...108 na i pdh photo current sensitivity outh pulse height to trigger internal threshold outh . refer to functional description sensh programmable between 60...144 na i pulse maximum input pulse current if the input current pulse is above this level, the recovery time t rec becomes t relax . (refer to parameter t relax ) 100 a i n_imin input related noise @ i pddc =0 15 na rms i n_imax input related noise @ i pddc =i pddcmax 20 na rms i pddc dc photo diode current generated by ambient light with no effect to the sensitivity 0.0 2 ma c pd photodiode capacitance refer to section application information, photodiode capacitance 50 pf t pulse led pulse length tpulse programmable between 18 s t cycle led cycle time for fork light barrier, standalone mode tper programmable between 5100'000 s for fork light barrier, controlled mode controlled by en input t relax recovery time after a strong current pulse (i pulse = 100a) 50 s t r response time minimum time from light beam detection to status change of the output outn or outh . t r_max = ( n v + 1 ) * t cycle refer to t cycle / n v programmable between 10s...3.3s t f release time (fall time) minimum time from beam interruption to status change of the output outn or outh . t f_max = ( n m + 1 ) * t cycle refer to t cycle / n m programmable between 10s...54.6min n v valid pulse counts number of weighted valid (non-missing) pulses to trigger the output. refer to functional description inc (programmable between 132 pulses) n m missing pulse counts number of weighted missing pulses to release the output. refer to functional description dec (programmable between 132'767 pulses) ? 2011 espros photonics corporation characteristics subject to change without notice 3 datasheet epc110 - v2.1 www.espros.ch
epc110 other parameters ( typical values, t amb = 25c, v dd = 3.3v) 0 1 2 3 4 5 6 40 50 60 70 80 90 100 110 120 pulse width [us] s e n s i t i v i t y [ n a ] figure 2 : input sensitivity vs. led pulse width ? 2011 espros photonics corporation characteristics subject to change without notice 4 datasheet epc110 - v2.1 www.espros.ch
epc110 connection diagrams top view cs outn so pd gnd vdd en si led sck vdd33 outh vdd18 3 2 1 10 5 4 7 6 8 9 pin connections qfn16-veed- 1vn4 lst 20.05.2011 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . pin connections qfn16-veed- 1vn4 lst top view 1 2 3 4 5 6 7 8 9 10 11 12 1 3 1 4 1 5 1 6 o u t n / s o o u t h c s pd gnd v d d v d d 1 8 v d d 3 3 led/ sck en/si n c _ g n d nc_gnd nc_gnd n c _ g n d nc_gnd nc_gnd 10-pin chip scale package (csp) 16-pin qfn package 10-pin csp 16-pin qfn pin name type description 1 9 vdd power supply positive power supply. operation mode: to be connect to vdd33. during command prog: to be connected to programming voltage. 2 7 gnd power supply negative power supply pin. 3 6 pd analog input photo diode input. 4 4 cs digital input terminated with internal pull up resistor light barrier: mode selection: cs = 1: operation mode (led, en, outn active) spi interface: chip select, cs = 0: command/program mode ( sck , si, so active) 5 2 outh digital output load depending light reserve detected - s ee figure 8 . refer to section light reserve output outh open drain output 6 1 outn so digital output open drain output light barrier: light pulses detected, amplified and filtered signal see functional description spi interface: serial data output 7 15 en si digital input terminated with internal pull up resistor light barrier: fork light barrier controlled mode: led pulse stimulation fork light barrier standalone mode: no function. spi interface: serial data input 8 14 led sck digital output digital input light barrier: output to led driver spi interface: serial input/output clock. for start/stop condition of spi communication (while cs = 1): set sck =1 and sck line in tristate mode (high ohmic) 12 vdd33 power supply positive power supply. 10 10 vdd18 decoupling pin for external filter/decoupling of the internal 1.8v supply: 4.7nf ceramic type not for supply of external circuits n/a 3, 5, 8, 11, 13, 16 nc_gnd not connected. connect this pins to gnd (guarding). ? 2011 espros photonics corporation characteristics subject to change without notice 5 datasheet epc110 - v2.1 www.espros.ch
epc110 functional description light barrier applications to cover different aspects of applications the epc110 device can operate in various modes: 1. standalone mode the led flashes in a predefined/programmed cycle time. 2. controlled mode together with a micro-controller the led pulse starts on the positive edge of the input en. the light is detected while the enable signal en is high. 3. fix-parameter mode this is the use of a pre-programmed parameter setting all the time. usually the programming takes place during configuration and test period of the board. 4. ambient adaptive reading by dynamic parameters in this mode the micro-controller is doing the parameter setting during the operation mode. for the communication the spi interface is used. for more technical de tails refer to chapter spi interface . application is for enhanced functionality and requirements as additional filtering of environmental ac light, adjustments of the sensitivity on the fly, controlling the led current by micro-processor, etc. example of a sensitivity control: the photo diode current is compared to two threshold levels. the result from the higher comparison ( outh ) may be used to regulate the led current as well the photodiode receiving parameters appropriate to the environmental conditions. light barrier application without an additional controller figure 3 : principle of standalone light barrier application figure 3 shows the epc110 in a light barrier application with minimal part count. the led flashes with a predefined rate. if the current of the light reflected (e. g. from a diffuse reflecting object or a retro reflector) to the photo diode at pin pd exceeds the threshold val ue i pdn , the output outn goes to the low state for a time which is longer than the time to the next led pulse. thus, the signal at the pin outn is constantly low when the photo diode generates a photo current which exceeds the threshold level. the stored flashing parameters of the led can be programmed using the spi interface described in this manual. the photo diode current is compared to two threshold levels. the result outh from the higher comparison level may be used to detect the light reserve. light barrier application using a micro-controller if additional functionality is required in a specific application, a micro-controller can be used. such additional requirements can be power saving modes, additional filtering of environmental ac light, counting purposes, etc. in this configuration, the led emits one light pulse on the positive edge at the pin en. the photo diode bias and amplifier chain is enabled while the enable signal en is high so a light pulse can be detected. ? 2011 espros photonics corporation characteristics subject to change without notice 6 datasheet epc110 - v2.1 www.espros.ch an epc100 light curtain transmitter lst vdd33 vdd epc110 gnd pd outn led gnd outn 24.01.2011 page 1 ... file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . c1 r stab d2 c2 r led vdd d1 outh outh
epc110 figure 4 : principle of controlled light barrier application using a micro-controller the photo diode current is compared to two threshold levels. the result outh from the higher comparison level may be used to detect the light reserve. evaluation of a single light pulse the photodiode is operated against ground and is reverse biased at a constant voltage of 1.2v. the input impedance of pin pd is kept low (<1 kohm @ 100khz) in order to minimize the influence of the parasitic capacitance of the photodiode. to ensure proper operation under high ambient-light conditions, the photo diode dc current can be up to 2 ma. the resulting current from the light pulses are converted to a voltage, filtered, amplified and compared to two different threshold levels. the lower threshold sensn (input related 60na typical) is used for the detection of the signal, the higher threshold sensh (input related to 96na typical) is used to provide an output when a certain signal reserve is achieved. to detect the received light pulse properly, the given threshold must be at least five times higher than the rms value of the noise floor generated by the circuitry without ac light stimulation. the comparator results are digitally filtered and output at pin out and outh . the parameter tper defines the scan period in the standalone light barrier application but has also an impact to the settling time of the receiver in the controlled mode application. it this case it has to be set corresponding to the scan period. refer to the description of the tper command. for each single light pulse, received and detected by the photodiode, the threshold levels for output outn and for output outh can be set by programming (parameter sensn resp. sensh) . they are processed according to the following principle to propagate the output signals outn and outh resp. outn int and outh int . as far the received light pulse signal exceeds the corresponding threshold level, the pulse will be recognized as a valid pulse and the detection circuit sets the appropriate output signal outn int or outh int . signal output outn light reserve outh i pd threshold levels: outn int light pulse detection light reserve detection i pd outh int t t t t t t figure 5 : pulse evaluation ? 2011 espros photonics corporation characteristics subject to change without notice 7 datasheet epc110 - v2.1 www.espros.ch an epc100 light curtain transmitter lst vdd33 vdd epc100 gnd outh pd outn en led gnd vdd c vdd out gnd in1 in2 en r stab r led out 11.02.2011 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . c1
epc110 pulse modulated operation (e.g. outn int to outn ) the epc110 chip operates the led and the receiver path on a pulse modulated concept. thus, the led is operated with short pulses whereas the receiver channel does synchronous demodulation of the received light pulses by reading the current pulses of the photo diode. this concept allows a very high sensitivity, high speed operation, and a high suppression of input ambient or foreign light (dc currents) generated by sunlight or other dc light sources like light bulbs. the pulse length is set by the parameter tpulse. in the standalone mode t he whole sys tem is clocked by the scan period defined by the programmed parameter tper. in the controlled mode the timing is propagated from the external sig nal en (positive edge, synchronized on the internal clock). in order to eliminate interference caused by modulated light, e.g. a flashing light or by other light barriers, the input signal from the photodiode is amplified, filtered, and processed by an integrated signal proc essor. if the photo diode signal meets the required frequency, pattern and amplitude, the output(s) are triggered. the following timing diagram shows the basic concept. emitter led beam interrupted photo diode current i pd no yes outn int or outh int t r 1 2 n m t f 1 2 n v t pulse t cycle outn or outh off on [ v ] response time valid (non-missing) p ulses release time missing pulses figure 6 : pulse modulation concept it is in fact a digital filter which counts missing and non-missing pulses to change the ou tput state of outn or outh . working principle of the digital filt er e.g. for the signal outn int to outn filter : the aim of this programmable filter is to suppress single pulses, so they cannot trigger the output and generate a false signals. this filter is based on a counter, which is counting up (increment) the valid pulses and counting down (decrement) the missing pulses in a weighted manner. separate weighting factors can be selected for valid pulses (parameter inc) and missing pulses (parameter dec). if the counter reaches the upper limit (maximum count, response time), the signal outn is set to low. s imilar in the opposite direction, if the counter reaches zero, the lower limit (minimum count, release time), the signal outn is put to high. with the parameters inc and dec the filter has the advantage of individual selectable gradients of the slopes. counter will never exceed maximum nor minimum limit. in between it acts as an integrator of both parameters. if pulse then C if pulse = valid then counter = counter + (inc * 1024 for inc > 0 and 32 * 1024 for inc = 0) if counter > 2 15 (maximum limit) then counter = maximum limit if counter = max imum limit then outn = 0 C if pulse = missing then counter = counter - (2 dec ) if counter < 0 (minimum limit) then counter = minimum limit if counter = minimum lim it then outn = 1 else wait for puls e lets assume that the photo diode does not receive light pulses for a long time: this means the light beam is interrupted. then outn is at high le vel. if the light beam is not anymore interrupted, the photodiode receives light pulses which are strong enough to trigger the outn int threshold and the internal pulse evaluation unit (designated in figure 5 with 'pulse evaluation') starts to count the receiving pulses. if the number of received pulses reach the set level n v , the output outn turns to low level. thus, single pulses cannot trigger the output and generate a false signal. the same procedure is used when a beam changes from not interrupted to interrupted. the internal pulse evaluation unit counts the missing pulses. if the number of missing pulses reaches the set level n m , outn is turned to high level. ? 2011 espros photonics corporation characteristics subject to change without notice 8 datasheet epc110 - v2.1 www.espros.ch
epc110 the same principle applies to the counter and signal of outh . the parameter inc defines the delay n v in number of clock cycles from the start of a pulse chain to the negative edge of outn . the parameter dec defines the delay n m from the end of a pulse chain to the positive edge of outn . application example no. of pulses n m no. of missing pulses n v long range 8 8 high speed 3 2 table 2 : example: settings based of filter coefficients inc and dec light pulse detection output outn the epc110 contains two digital outputs to indicate that a valid signal of light pulses are received by the photo diode. the first output outn is triggered, when the lower threshold is reached by the input signal (see figure 5 ). this output is used usually to drive the output of the light barrier. this is a fully cmos compatible digital output. light reserve output outh however, if the incoming signal is just at the trigger threshold of outn , an unstable situation can occur. thus, a second output outh is integrated with a higher trigger threshold to indicate that a certain 'light reserve' is reached (see figure 5 ) . this output is usually used to drive a visible led to indicate to the operator a stable detection function of the light barrier. to have not too short pulses outh, this signal is stimulated by signal outh filter and synchronized reseted by outn . outn filter outh filter outn outh emitter led figure 7 : synchronization outh with outn the trigger threshold of outh is set usually approx. 50% above the trigger threshold of outn . this output is not cmos compatible . its voltage is depending of the load according to figure 8 . file: unbenannt this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . outh high min.: 3.0v / + 85 o c outh high max.: 3.6v / - 40 o c outh high typ. outh low max. voltage outh [ v ] c u r r e n t o u t h [ m a ] figure 8 : output voltage versus output current of output outh ? 2011 espros photonics corporation characteristics subject to change without notice 9 datasheet epc110 - v2.1 www.espros.ch
epc110 to have still digital compatible signals a level conversion is necessary. below you find some examples for such circuits for converting outh levels to full cmos compatible digital output. <name> file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . 24.01.2011 page 1 <xx> outh led outn pd vdd33 vdd epc110 gnd vdd18 gnd +3.3v outh r1 3k6 r2 12k r4 10k r3 4k7 t1 bc846 b figure 9 : non-inverting, low power level shifter (additional current approx. 0.6ma) <title> <name> file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . 24.01.2011 page 1 <xx> outh led outn pd vdd33 vdd epc110 gnd vdd18 gnd +3.3v outh r1 1k5 r3 33k t1 bc846 b r2 10k <title> <name> file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . 24.01.2011 page 1 <xx> outh led outn pd vdd33 vdd epc110 gnd vdd18 gnd +3.3v outh r1 3k6 r2 12k r4 22k r3 4k7 t1 bc846 b r5 33k t2 bc846 b figure 10 : simple inverting level shifter (additional current approx. 1.6ma or 2.6ma) figure 11 : inverting, low power level shifter (additional current approx. 0.8 ... 1.0ma) ? 2011 espros photonics corporation characteristics subject to change without notice 10 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 parameters the parameters are defining the functionality of the epc110. the big variety of possible settings allows to cover a wide range of applications. the devices contains a memory to store the application parameters. they are stored into 16bit registers. the registers are organized into 2 blocks: a volatile and a non-volatile one. parameter memory organization (epc110) the following classes of data are stored for each device: ? application parameters ? unique chip id and chip adjustments (factory set) this data can be permanently stored in a read-only memory (rom) 1 and is mirrored in a volatile memory (ram). at power up, the data (except the chip id) is copied from the rom to the ram. during operation, the data from the ram is used. both memories are organized in 16 registers at 16 bits each. the data can be accessed on a 16-bit register base. if a register has been burned (=stored into the rom) the first bit is set: fusebit = 1. if vmod = 1 is selected, the register cannot be modified any more nor in ram nor in rom area. for vmod = 0 the ram area is still accessible. so far the chip can be operated in two different modes: ? fix-parameter mode vmod = 1: e.g. as standalone or pre-configured device operated with not modifiable data from ram, which are stored permanently in rom. ? dynamic mode vmod = 0: e.g. for adaptive systems, dynamic systems operated with modifiable data from ram. the spi interface allows to modify these data in the ram area at any time on the fly. at power up these data are loaded from the permanent stored data in the rom. if the run-time configuration differs from the data set stored in the rom, it has to be restored after each power-up again by the external micro-processor over the spi interface. the following table shows the memory organization: non-volatile memory address range (register no.) volatile memory address range (register no.) description 0 - 3 16 - 19 application parameters 4 - 6 20 - 22 trim values, factory set 7 23 device address (not applicable) 8 - 15 - chip id, factory set - 24 - 31 for factory test purpose. read only. table 3 : memory map overview as shown in the table above, registers 0 C 3 are used for configuring the chip in the application. before the devices can be used in a final light- barrier system, the required application parameters of the chip in the system have to be stored into the device memory. the following table shows the allocation of the available parameters in the memory of the epc110: bit # rom ram 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r e g i s t e r # 0 16 vmode mode 1 0 0 0 0 0 0 tpulse pol fusebit 1 17 tper dec 0 0 inc 0 0 fusebit 2 18 0 0 0 0 1 0 1 0 1 sensh sensn fusebit 3 19 don't use fusebit 4 20 don't use fusebit trimming 5 21 don't use fusebit 6 22 don't use fusebit 7 23 don't use fusebit device address 8 24 lot no. lsb fusebit chip id 9 25 lot no. msb fusebit 10 26 chip id fusebit 11 27 factory use only fusebit 12 28 revision no. fusebit 13 29 no function fusebit 14 30 no function fusebit 15 31 no function fusebit application parameters figure 12 : detailed memory map epc110 1 the non-volatile memory is a one-time-programmable memory (otp). once the memory is programmed, the programmed values cannot be overwritten anymore. ? 2011 espros photonics corporation characteristics subject to change without notice 11 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 parameter settings can be done by writing complete 16 bit registers only. bits marked up in white fields shall be modified or programmed only. gray marked bits with a given value in the memory map above must be set to this. never change the memory content of gray marked cells without numeric indication. writing to this cells is not allowed. the ram can be written only, if the corresponding rom memory hasnt been written before (fusebit = 0) or if the volatile mode is active (vmode = 0). the first bit of each 16-bit rom register serves as write inhibit bit (fusebit). to write to the rom, the micro-controller has to write the data to the ram first (with fusebit = 0). from there, the micro-controller can first double check the data integrity. when a memory section is verified, the content can be transferred from the ram memory to the rom using the command prog (refer to chapter command prog ). while processing this instruction the fusebit will be set to 1 by epc110. the device is fully operational as well without programming the rom, but data will be lost at power down. operating the chip in this mode is helpful during the development of the product or if your application needs an adaptive mode. however, in the final application for a standalone or self-reboot operation, the parameters must be stored into the rom memory. parameter description (epc110) parameter name register no. bit no. function rom ram fusebit 0 16 0 during write operation to this ram register, put this bit = 0. this bit will be se t automatically, when corresponding rom register is prog rammed . 0 values 0 the corresponding rom register is not programmed 1 the corresponding rom register is programmed pol 0 16 1 polarity of the led pulse. setting is depending on the led driver circuitry. 1 values default recommended setting 0 active low x 1 active high x tpulse 0 16 4...2 pulse length t pulse of the light pulse 4 3 2 values default recommended setting 0 0 0 1s x 0 0 1 2s x (typical setting) 0 1 0 3s 0 1 1 4s 1 0 0 5s 1 0 1 6s 1 1 0 7s 1 1 1 8s n/a 2 18 11...5 no function, must be set as listed below 11 10 9 8 7 6 5 1 0 0 0 0 0 0 mode 0 16 14...12 definition of operation mode. 14 13 12 value 1 0 1 fork light barrier, standalone mode: led pulse and light detection reading generated internally. 0 1 1 fork light barrier, controlled mode: externally stimulated led pulse by positive edge of signal on pin en. externally controlled light detection by signal on pin en=1. x x x all other settings forbidden. function of the device not defined and guaranteed. ? 2011 espros photonics corporation characteristics subject to change without notice 12 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 vmode 0 16 15 disables write access to volatile ram 11 values default recommended setting 0 on x write access to ram possible. 1. fix-parameter mode / debug mode: this setting allows to overwrite the ram contents, which is useful during debugging. once the system is fully developed, this parameter should be set to 1. 2. dynamic mode: this setting could also be useful for dynamic system application, if the system parameters should be changed on the fly after power-up. it is recommended to program the parameters and burn it into the rom first. all deviating run-time parameters have then to be downloaded on the fly after power-up every time. 1 off write access to ram denied. set to 1 in the final product to avoid accidentally overwriting of the contents of the ram registers. parameter name register no. bit no. function rom ram fusebit 1 17 0 during write operation to this ram register, put this bit = 0. this bit will be set automatically, when corresponding rom register is programmed. 0 values 0 the corresponding rom register is not programmed 1 the corresponding rom register is programmed n/a 1 17 2...1 no function, must be set to 0 2 1 0 0 inc 1 17 6...3 weight of valid pulse counts. refer to pulse modulated operation (e.g. outnint to outn) : minimum number of valid (non-missing) pulses n v of light detection for counting the r esponse time t r . 6 5 4 3 inc min. n v setting 0 0 0 0 0 1 x (default setting) 0 0 0 1 1 32 0 0 1 0 2 16 0 0 1 1 3 11 0 1 0 0 4 8 x (typical setting) 0 1 0 1 5 7 0 1 1 0 6 6 0 1 1 1 7 5 1 0 0 0 8 4 1 0 0 1 9 4 1 0 1 0 10 4 1 0 1 1 11 3 1 1 0 0 12 3 1 1 0 1 13 3 1 1 1 0 14 3 1 1 1 1 15 3 n/a 1 17 8...7 no function, must be set to 0 8 7 0 0 ? 2011 espros photonics corporation characteristics subject to change without notice 13 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 dec 1 17 12...9 weight of missing pulse counts. refer to pulse modulated operation (e.g. outnint to outn) : minimum n umber of missing pulses n m of light detection for counting the r elease time (fall time) t f . 12 11 10 9 dec min. n m setting 0 0 0 0 0 32768 x (default setting) 0 0 0 1 1 16384 0 0 1 0 2 8192 0 0 1 1 3 4096 0 1 0 0 4 2048 0 1 0 1 5 1024 0 1 1 0 6 512 0 1 1 1 7 256 1 0 0 0 8 128 1 0 0 1 9 64 1 0 1 0 10 32 1 0 1 1 11 16 1 1 0 0 12 8 x (typical setting) 1 1 0 1 13 4 1 1 1 0 14 2 1 1 1 1 15 1 tper 1 17 15...13 for fork light barrier, standalone mode: led cycle time t cycle . for fork light barrier, controlled mode: select next lower value then external en cycle time. 15 14 13 values default recommended setting 0 0 0 5s x 0 0 1 10s 0 1 0 30s 0 1 1 100s x (typical setting) 1 0 0 300s 1 0 1 1ms 1 1 0 10ms 1 1 1 100ms parameter name register no. bit no. function rom ram fusebit 2 18 0 during write operation to this ram register, put this bit = 0. this bit will be set automatically, when corresponding rom register is programmed. 0 values 0 the corresponding rom register is not programmed 1 the corresponding rom register is programmed sensn 2 18 3...1 lower threshold setting of the p hoto current sensitivity i pdn to trigger output outn . 3 2 1 values default recommended comments 0 0 0 24na x a lower value increases the sensitivity. a too sensitive setting leads to false readings because of shot noise of the receiver photo diode and the internal amplifier (typ. input noise level is 7na rms without photo diode). also induced emi can lead to false readings if the sensitivity is set too low. the emi sensitivity is heavily depending on the system architecture and the electromechanical design. the better the shielding of the chip and the photo diode and the better the pcb layout, the better the emi immunity. the tolerance of the threshold is approx. 25%. 0 0 1 36na 0 1 0 48na 0 1 1 60na x 1 0 0 72na 1 0 1 84na 1 1 0 96na 1 1 1 108na ? 2011 espros photonics corporation characteristics subject to change without notice 14 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 sensh 2 18 6...4 upper threshold setting of the p hoto current sensitivity i pdh . to trigger output outh . 6 5 4 values default recommended recommended setting 0 0 0 60na x common use is to set this value 50% above the value used at sensn, i.e., if sensn is put to 48na, set sensh to 72na. the tolerance of the threshold is approx. 25%. 0 0 1 72na 0 1 0 84na 0 1 1 96na x 1 0 0 108na 1 0 1 120na 1 1 0 132na 1 1 1 144na n/a 2 18 15...7 no function, must be set as listed below 15 14 13 12 11 10 9 8 7 0 0 0 0 1 0 1 0 1 sample parameter setting in the section applications you will find programming examples for long range light barrier application (refer also to datasheet epc111) and for high speed detection rate design (refer also to datasheet epc112) . ? 2011 espros photonics corporation characteristics subject to change without notice 15 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 spi interface the serial peripheral interface (spi) allows the micro-controller to communicate with the epc110 device. it allows the access to the internal memory of the chip for parameter setting and programming for configuration or in a dynamic mode to change parameters on the fly. hardware interface this functionality is given by double-used pins: led/ sck , en/si, outn /so. the signal cs does t he s election, if the operation mode or the command/program mode is active: 1. cs = 1: operation mode led, en, outn are active. 2. cs = 0: command/program mode sck , si, outn are active. as long as cs = 0 the pin led/ sck is set to high-ohmic and defined as input pin. important notice: due to fact of the advantage of the flexibility in use of this devic e the responsibility of any possible hardware, led load or led driver conflicts have to be handled by the user and are depending of the final application schematic. main items to take care of are: ? double-use as input as well output of led/ sck signals/line. for non-standalone application a well done decoupling of the signals is needed. ? parameter setting and programming of the device in final application environment e.g. if led and led drivers are not designed for continuous mode application, risk of overloading. ? during spi access of the device in final application environment e.g. if led and led drivers are not designed for continuous mode application, risk of overloading. possible solutions are discussed at the example of the principal schematic figure 13: hardware interface micro-controller C epce110 . <title> file: unbenannt this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . 25.01.2011 page 1 <xx> lst vdd c + c1 r2 vled t1 d1 r1 buf1 inv1 and1 v_in v_out adj regulator 3.3v led/ sck en/si outn /so outh cs vdd33 vdd18 pd gnd vdd epc110 gnd vdd prog sck so si cs gnd vdd controller out esck in r4 r3 r5 t3 t2 t4 out prog d4 8v2 r7 d2 d3 r6 r8 s1 figure 13 : hardware interface micro-controller C epce110 1. mode selection: operation mode - parameter/program mode as long the device is not connected to an led driver, the access to the spi interface is allowed while cs = 0. this can simply be done by the switch s1 before power up the circuit. in this case the output led/ sck will not be driven as an output. 2. run-time access of spi interface t o have no conflicts together with a micro-processor on the bus line led/ sck (output/input) during run-time operation in this example, the decoupling and interfacing of the led/ sck line is done by the tristate buffer buf1, the additional input in and additional output enable sck (out esck). while the led is in operation, driven by the epc110, out esck = 0 will tristate the buffer and the sck line from the micro-processor. with the input in the micro-processor can read the status of the led/ sck line after the buffer for finding the correct transition time. ? 2011 espros photonics corporation characteristics subject to change without notice 16 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 signal conditions and sequences: operation mode: cs = 1, sck =1, buf1 = tristate (out esck = 0), led/ sck toggling by epc110. mode transition to spi: if led/ sck = 1 : sck =1, buf1 = transparent (out esck = 1), cs = 0. parameter/program mode: cs = 0, buf1 = transparent (out esck = 1), sck and led/ sck toggling by micro-processor. mode transition to operation: if led/ sck =1: buf1 = tristate (out esck = 0), cs = 1. 3. overload-protection of led and led driver are the led and led driver not designed for continuous mode operation, there is a risk of overloading the led or the led driver in case of no decoupling of the led driver input from the spi interface as well from the command instructions. the signals on the line led/ sck are depending of the status of the sck signal itself and from the commands polarity of led pulse pol, pulse length tpulse, mode selection mode and the status of the line en. in the example circuitry this decoupling is done by the signal out esck, the inverter inv1 and the and-circuit and1. in case of switching the buffer buf1 transparent (out esck =1) the led driver signal is set to low. 4. supply of the programming voltage (vprog 7.5v) at pin vdd (refer also to chapter programming procedure ) to write the data from the volatile ram section to the non-volatile rom section a programming voltage has to be connected to the vdd pin of the epc110 following the timing diagram of figure 17: direct programming procedure . this is done by an overwriting voltage source to the vdd pin in the proposed design. the main supply for he micro-processor and the epc110, pin vdd33 is done by the 3.3v voltage regulator, the diode d3 and the resistors r3 and r4. pin vdd of the epc110 is fed by diode d2. this allows to overwrite the 3.3v operating supply by the higher 7.5v programming voltage. the programming voltage is produced by the voltage regulator t3, d4 and r6. switch on/off of the programming voltage will be done by the r7,t4,r5 and t2 and the signal out prog. timing specifications of telegrams while cs = 0 and serial clock sck is toggling in bi-directional function data are C on input si read in (command) with the positive edge and C on output so read out (result) with the negative edge of the serial clock. means whilst data are sent to the epc110 chip by the micro-controller, in parallel the result of the last (or more generally: of a previous) command is sent back from the epc110 to the micro-controller according to the spi protocol. the timing diagram is shown in figure 14 ). part name part no. designed approved scale page <partname> <x000 000> <name> <data> m 1:1 <name> t h i s d o c u m e n t i s c o n f i d e n t i a l a n d p r o t e c t e d b y l a w a n d i n t e r n a t i o n a l t r a d e s . i t m u s t n o t b e s h o w n t o a n y t h i r d p a r t y n o r b e c o p i e d i n a n y f o r m w i t h o u t o u r w r i t t e n p e r m i s s i o n . file: 26.02.2009 1 <xx> din a4 sck sck cs si so t h 1/f sck t l t hold t su t d t 1 t rf sck t rf cs si so serial input/output clock C positive edge: data read in; negative edge: data read out device selection serial data input serial data output raster 2.5 x 2.5mm figure 14 : spi bus timing ? 2011 espros photonics corporation characteristics subject to change without notice 17 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 symbol parameter comments / conditions values units min. typ. max. t 1 edge time cs to sck falling edge cs to falling edge sck 50 ns f sck clock frequency of sck 10 mhz t h / t l high and low period of sck 50 ns t su / t hold set-up and hold time of si data stable before and after positive edge of sck 15 ns t d output data of so valid data valid after negative edge of sck 20 ns t rf / t rf sck rise / fall time so / sck 20 ns input data format and command list the communication is based on telegrams (direct commands or results), which are sent and received over the spi interface. the input data format (telegram) is given in figure 15 . the first bit in the data stream from the microprocessor to the epc110 chip (si pin) will be b = 0 always. figure 15 : communication to the epc110 device: direct command command set: name cmd code start b cmd code command c0...c2 cmd code extension r0...r4 cmd code data d0...d16 cmd code termination t0, t1 function result data no. of data bits on spi interface command / result nop 0 000 --- --- --- no operation, or read out data no R 4 read 0 010 register address --- 00 read register rn yes 11 / 22 write 0 011 register address data 00 write data to ram (register 16...18) no 27 / -- prog 0 110 register address --- --- copy data to rom no 9 / -- reset 0 111 11001 --- --- reset the device no 9 / -- table 4 : command list remarks : ? the telegram data is transmitted with the lsb first. ? a telegram starts with the cs change from high to low (synchronization) and ends with the change from low to high. ? single telegrams either commands as well results have to be separated by a cs = 1 in between. ? additional sck clock cycles have no effect. this allows to extend the above given minimal telegram lengths to a standardized telegram lengths (byte, word or double-word). ? the minimum te legram length is given in table 3 , section number of d ata bits. ? 2011 espros photonics corporation characteristics subject to change without notice 18 datasheet epc110 - v2.1 www.espros.ch <spi direct command> <lst> 20.05.2011 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . cs sck si c0 c1 c2 r0 r1 r2 r3 r4 d0 d1 dn command register address or cmd extension data b t0 t1
<br> epc110 detailed command & result descriptions command nop: no operation the command nop can be used to fetch data without sending a new command C see next section readout of returned results . readout of returned results the results/data at output pin so depend on the previous transmitted command to input pin si. two ways to readout this data are possible: 1. either it can be fetched in parallel of transmitting a next command 2. or by sending nop commands just by toggling sck while cs is low. remarks: ? the data is represented with the lsb first. ? data is valid on positive edge of clock sck while cs is low. ? if more clock toggles sck are issued than data can be fetched, zeros are transmitted. command read: read register rn with the command read the registers of the ram and rom memory can be read register by register. the command extension register address defines the requested register for reading it out. after command transmission the expected result data can be readout on the so pin. result readout frame (telegram): figure 16 : timing result data result data format: data bits function n not used, have to be ignored r0...r4 5 bit register address d0...d15 16 bit returned data of the corresponding register (one complete register) table 5 : result of a read command command write: write to ram register 16 - 18 data can be written into the volatile ram register 16 C 18 by using the command write. the command extension register a ddress selects the register. it is followed by the data to be written. in vmod = 1 it is possible to write to registers only, if the corresponding register in the rom has not been written yet. it is not possible to write directly to a rom register. if the data has to be stored into the rom register, a subsequent command prog has to be used. in vmod = 0 the ram registers can be written at anytime. command prog t he command prog transfers the data from the ram register to the corresponding rom register. see chapter parameter programming for a detailed description. command reset the command reset resets the device and initiates a startup. ? 2011 espros photonics corporation characteristics subject to change without notice 19 datasheet epc110 - v2.1 www.espros.ch <timming spi read command 1> <lst> 24.01.2011 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . cs sck so n r0 r1 r2 r3 r4 d0 dn
<br> epc110 parameter programming general description a description of the hardware interface for programming is given in chapter hardware interface . the device is initially not parametrized. in order to operate the light barrier, the micro-controller (or programmer) needs to do the correct parameter settings for the selected functionality. this step is usually done in the factory of the light barrier manufacturer. after this the micro- controller can operate the light barrier or it can work in a standalone mode. to do so, a specific parametrization of the devices must be executed first. the following procedure is an example thereof. no. step description 1 set parameters parameters like pol, tpulse, mode, vmode, inc, dec, tper, sensn, sensh are stored into the ram of the device using the command write. write them register by register. 2 check parameters the parameters should be checked by reading them back from each device using the read command. 3 program parameters if all parameters are stored correctly, store the parameters into the non-volatile memory by using the command prog. please refer to chapter programming procedure . 4 final test to check the programming of the parameters, turn off the power supply and readout all parameters again. programming procedure programming the device is a transfer of the data from the ram to the corresponding rom register. each 16-bit register must be transferred individually. thus, register 16 is transferred to register 0, register 17 to register 1, register 18 to register 2. all other registers must not be used. figure 12 shows the timing of the programming sequence for one register: prog is the prog command sequence (110). register means the address of the target register (rom), e.g. 0, 1, 2. during programming the voltage at pin vdd has to be increased to vprog ( 7.5v) and has to be kept stable buffered during the whole programming cycle. for an example of a hardware design to generate this supply refer to chapter hardware interface in the spi interface section. the timing parameters given in figure 17 have to be obeyed. remarks: ? it is possible to program more than one register during a vdd high cycle. between two prog commands a delay of 400s is needed. ? each register can be programmed once only (rom). ? after programming a register, bit no. 0 of this register becomes automatically a one to indicate that the register is programmed (fusebit). ? 2011 espros photonics corporation characteristics subject to change without notice 20 datasheet epc110 - v2.1 www.espros.ch figure 17 : direct programming procedure r0 r1 r2 r3 r4 sck cs vdd si 400s 50s 3.3v 7.5v prog register 1 1 0 b
<br> epc110 applications long range light barrier application (refer also to datasheet epc111) figure 18 shows the epc110 as an example in a long range light barrier application with minimal part count. the led flashes according to the description of the previous chapter. light of the led is passing either direct, reflecting from a reflecting object or a retro reflector to the photo diode pd. if the received light fulfills the criteria according to the description in the previous chapter, the output signals outn and outh are set. led driver: the output led of the epc110 to drive the led driver circuit is a current source capable to drive typically 1ma. for a high performance long range light barrier (>8m), an led peak current of up to 1.5a is needed. to generate such a high led current, an external driver circuit is necessary. the circuitry in figure 18 is a simple implementation of such a driver circuit. the darlington circuit with t2 and t3 and r2 and r3 does the job. in order to avoid interference on the supply voltage, the supply is isolated (filtered) with r1 and c1. the high peak led pulse current is delivered by the capacitor c1, which itself is charged by r1. make sure, that there is no coupling of the high led current to the ground of the epc110 or to the cathode of the photo diode. this driver circuit operates with a vdd led in a range of 10 to 30 vdc. <title> <name> file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . 25.01.2011 page 1 <xx> outh led outn pd vdd33 vdd epc110 gnd vdd18 r3 1r2 c1 47f low esr gnd +3.3v vdd led = +24v outh outn pd epc300 t2 bc846 r2 1k r5 3k6 r4 10k ir led tsml1000 r1 100r c3 100nf c2 1 f c5 4.7nf c4 100nf r6 12k r8 10k r7 4k7 t1 bc846 t3 bcp56 marked conductors must be short and low ohmic c2 the epc111 device with its very sensitive input pd needs a well decoupled power supply figure 18 : long range light barrier application with minimal part count notice: the schematic is for illustrating the basic circuit idea only. for the real built up the designer has to take all other additional influence factors in consideration too e.g. design rules, power rating, heat dissipation, ... rom ram 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r e g i s t e r # 0 16 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 fusebit 1 17 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 fusebit 2 18 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 fusebit 3 19 don't use fusebit 4 20 don't use fusebit trimming 5 21 don't use fusebit 6 22 don't use fusebit 7 23 don't use fusebit device address 8 24 lot no. lsb fusebit chip id 9 25 lot no. msb fusebit 10 26 chip id fusebit 11 27 factory use only fusebit 12 28 revision no. fusebit 13 29 no function fusebit 14 30 no function fusebit 15 31 no function fusebit application parameters figure 19 : corresponding memory map epc110 long range parameter settings can be done by writing complete 16 bit registers only. ? 2011 espros photonics corporation characteristics subject to change without notice 21 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 high speed detection rate design (refer also to datasheet epc112) figure 20 shows the epc 110 as an example in a high speed detection rate light barrier application with minimal part count. this design is optimized for a fast reading of light beam interruptions. where as the working principle is similar to the above example. this driver circuit operates with a vdd led in a range of 6 to 20 vdc. <title> <name> file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . 25.01.2011 page 1 <xx> outh led outn pd vdd33 vdd epc110 gnd vdd18 r2 13r c1 10f low esr gnd +3.3v vdd led = +12v outh outn pd epc300 r4 3k6 r3 10k r1 47r c3 100nf c2 1 f c5 4.7nf c4 100nf r5 12k r7 10k r6 4k7 marked conductors must be short and low ohmic ir led tsml1000 t1 bc846b t2 bc846b c2 the epc112 device with its very sensitive input pd needs a well decoupled power supply figure 20 : high speed detection rate light barrier application with minimal part count notice: the schematic is for illustrating the basic circuit idea only. for the real built up the designer has to take all other additional influence factors in consideration too e.g. design rules, power rating, heat dissipation, ... the following table shows the parameter allocation in the memory: rom ram 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r e g i s t e r # 0 16 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 fusebit 1 17 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 fusebit 2 18 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 fusebit 3 19 don't use fusebit 4 20 don't use fusebit trimming 5 21 don't use fusebit 6 22 don't use fusebit 7 23 don't use fusebit device address 8 24 lot no. lsb fusebit chip id 9 25 lot no. msb fusebit 10 26 chip id fusebit 11 27 factory use only fusebit 12 28 revision no. fusebit 13 29 no function fusebit 14 30 no function fusebit 15 31 no function fusebit application parameters figure 21 : detailed memory map epc110 high speed parameter settings can be done by writing complete 16 bit registers only. ? 2011 espros photonics corporation characteristics subject to change without notice 22 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 design precautions: emc shielding the sensitivity at pin pd is very high in order to achieve a long operation range of light barriers even without lenses in front of the ir led and/or the photo diode. thus, the pin pd is very sensitive to emi. special care should be taken to keep the pcb track at pin pd as short as possible (a few mm only!). this track should be kept away from the ir led signal tracks and from other sources which may induce unwanted signals. it is strongly recommended to cover the chip, the photodiode and all passive components around the chip with a metal shield. a recommended part is shown in figure 22 . t he pins at the bottom are to solder the shield to the pcb with electrical connection to gnd . the hole in the front is the opening window for the photo diode. the backside of the pcb below the sensitive area (pd, epc110) shall be a polygon connected to gnd to shield the circuit from the backside as well. ambient light photodiode dc current can be generated by ambient light, e.g. sunlight. dc current at pin pd does not generate a dc output signal. however, if i pddc is above the stated maximal value, the input is saturate d. this bloc ks the detection of ac current pulses. photodiode capacitance if the photo diode capacity is above the specified value, a lower detection sensitivity and a possible higher sensitivity spread results. ? 2011 espros photonics corporation characteristics subject to change without notice 23 datasheet epc110 - v2.1 www.espros.ch figure 22 : recommended emc shield
<br> epc110 layout information (all measures in mm, <partname> <x000 000> <name> <data> m 1:1 din a4 <name> part name part no. designed approved scale page t h i s d o c u m e n t i s c o n f i d e n t i a l a n d p r o t e c t e d b y l a w a n d i n t e r n a t i o n a l t r a d e s . i t m u s t n o t b e s h o w n t o a n y t h i r d p a r t y n o r b e c o p i e d i n a n y f o r m w i t h o u t o u r w r i t t e n p e r m i s s i o n . file: unben annt 1 26.02.2009 ) csp-10 package 0 . 5 1.9 +0.0/-0.1 1 . 4 + 0 . 0 / - 0 . 1 0.5 0.5 0.15 0 . 1 5 0 . 5 solder balls sn97.5ag2.5 0 . 3 0 . 1 1 0 . 0 1 ? 0.12 bottom view pin 1 <title> <name> 19.01.2012 page 1 file: this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . no solder mask inside this area 0.5 0.5 0 . 5 ? 0.3 2.5 2 . 0 0.1524 n o s o l d e r m a s k i n s i d e t h i s a r e a figure 23 : csp10: mechanical dimensions figure 24 : csp10: layout recommendation recommendations for reliable soldering of solder balls: ? use a pad layout similar as given in figure 24 . notice that all tracks should go underneath the solder mask area. ? do not connect any pins direct pin to pin inside of the opening of the solder mask. ? in case of the conductors are with a au-ni surface finish the preferred landing pad design for the solder balls will be covering the round landing pad with a gold surface finish as a solderable area only. qfn-16 package pin connections qfn16-veed- 1vn4 lst 25.01.2011 page 1 file: unbenannt this document is confidential and protected by law and international trades. it must not be shown to any third party nor be copied in any form without our written permission . pin connections qfn16-veed- 1vn4 lst top view 1 2 3 4 5 6 7 8 9 10 11 12 1 3 1 4 1 5 1 6 o u t n / s o o u t h c s pd gnd v d d v d d 1 8 v d d 3 3 led/ sck en/si n c _ g n d nc_gnd nc_gnd n c _ g n d nc_gnd nc_gnd opening in solder mask conductor layout shielding of pd pin figure 25 : qfn-16 : layout recommendation ? 2011 espros photonics corporation characteristics subject to change without notice 24 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 top view 2 . 9 - 3 . 1 2.9 - 3.1 1.9 0.25 0.5 0 . 9 bottom view 0 . 2 5 1 . 9 0.3 0 . 1 - 0 . 2 0 . 0 2 figure 26 : qfn-16: mechanical dimensions reflow solder profile for infrared or conventional soldering the solder profile has to follow the recommendations of ipc/jedec j-std-020c (min. revision c) for pb-free assembly for both types of packages. the peak soldering t emperature (t l ) should not exceed +260c for a maximum of 4 sec. ? 2011 espros photonics corporation characteristics subject to change without notice 25 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 packaging information (all measures in mm) tape & reel information the devices are mounted on embossed tape for automatic placement systems. the tape is wound on 178 mm (7 inch) or 330 mm (13 inch) reels and individually packaged for shipment. g eneral tape-and-reel specification data are available in a separate data sheet and indicate the tape sizes for various package types. further tape-and-reel specifications can be found in the electronic industries association (eia) standard 481-1, 481-2, 481-3. pin 1 8 pin 1 1 2 8 2 csp6 tape qfn16 tape pin 1 8 pin 1 1 2 8 4 csp6 tape qfn16 tape figure 27 : csp10 and qfn16 tape dimension. parts are placed with solder pads on bottom side espros photonics ag does not guarantee that there are no empty cavities. thus, the pick-and-place machine should check the presence of a chip during picking. ordering information type package rohs compliance packaging method epc110-csp10 csp10 yes reel <a href='http://www.datasheet.hk/search.php?part=epc110-qfn16&stype=part'>EPC110-QFN16</a> qfn16 yes reel ? 2011 espros photonics corporation characteristics subject to change without notice 26 datasheet epc110 - v2.1 www.espros.ch
<br> epc110 important notice espros photonics ag and its subsidiaries (epc) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to epcs terms and conditions of sale supplied at the time of order acknowledgment. epc warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with epcs standard war - ranty. testing and other quality control techniques are used to the extent epc deems necessary to support this warranty. except where man - dated by government requirements, testing of all parameters of each product is not necessarily performed. epc assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using epc components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. epc does not warrant or represent that any license, either express or implied, is granted under any epc patent right, copyright, mask work right, or other epc intellectual property right relating to any combination, machine, or process in which epc products or services are used. information published by epc regarding third-party products or services does not constitute a license from epc to use such products or services or a war ranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from epc under the patents or other intellectual property of epc. resale of epc products or services with statements different from or beyond the parameters stated by epc for that product or service voids all express and any implied warranties for the associated epc product or service. epc is not responsible or liable for any such statements. epc products are not authorized for use in safety-critical applications (such as life support) where a failure of the epc product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of epc products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by epc. further, buyers must fully indemnify epc and its representatives against any damages arising out of the use of epc products in such safety-critical applications. epc products are neither designed nor intended for use in military/aerospace applications or environments unless the epc products are spe - cifically designated by epc as military-grade or "enhanced plastic." only products designated by epc as military-grade meet military specific - ations. buyers acknowledge and agree that any such use of epc products which epc has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. epc products are neither designed nor intended for use in automotive applications or environments unless the specific epc products are desig - nated by epc as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, epc will not be responsible for any failure to meet such requirements. ? 2011 espros photonics corporation characteristics subject to change without notice 27 datasheet epc110 - v2.1 www.espros.ch
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